Register Allocation and Instruction Scheduling for an Efficient Retargetable Compiler
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Abstract
System designers increasingly employ compilers not only for pure application programming after an ASIP’s architecture is fixed but also for architecture exploration. During exploration, the designer tunes the initial architecture for a given application or application set. This tuning requires an iterative, profiling based methodology, by which the designer evaluates the cost-performance ratios of many potential architecture configurations. If C or C++ application programming is intended, the designer should apply a compiler-in-the-loop type of architecture exploration, thus avoiding a compiler and architecture mismatch. The compiler designers often have difficulty ensuring good code quality because an instruction set designed primarily from a hardware designer’s viewpoint fails to support their efforts. This problem is taken care by retargetable compilers. These compilers take processor description as input so that the machine code can be generated according to this description. Like traditional compilers, the code quality of retargetable compilers depends on the back end of the compiler. This paper describes a new register allocation and instruction scheduling technique.
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KeyWords : ASIP Design, Retargetable compilers, register allocation , instruction scheduling.
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