Redundancy for Fault Tolerance Algorithm in FPGA Architecture for Reliability with a BIST Approach

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Ms. Shweta S. Meshram
Ms. Ujwala A. Belorkar


In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault
tolerance. The decreasing feature sizes resulting from the improvement in the fabrication techniques has resulted in chips with very high device
count. Redundancy based hardening techniques are applied at the pre-synthesis or synthesis level. To provide solutions for increasing the faulttolerance
capabilities with algorithms able to reduce sensitive configuration memory bits of FPGAs we use BIST method. If nano-technology
fabrication are applied the yield may go down to zero as avoiding defect during fabrication will not be a feasible option Hence, feature
architecture have to be defect tolerant. We presented a new approach for testing FPGA’s by utilizing their reprogrammability. It gives solution in
which configuration bit-stream of FPGA is modified by a hardware controller with BIST that is present on the chip itself.



Keywords: Redundancy, Fault Tolerance, FPGA, Altera, BIST, Defect.


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