RF mixer design for 10.5 GHz, using 0.18μm CMOS technology

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Ms. Archana O. Vyas
Ms. Ujwala A. Belorkar


This paper present area efficient design for 10.5 GHz RF mixer using 0.18μm CMOS technology. VLSI Technology includes process design, trends, chip fabrication, real circuit parameters, circuit design, electrical characteristics, configuration building blocks, switching circuitry, translation onto silicon, CAD, practical experience in layout design. The proposed mixer is designed using 0.18μm CMOS/VLSI technology, which can be used in front end of a superheterodyne receiver. Simulations were performed using the Agilent advance designing software, TSMC model. Results indicate that mixer provides gain of 13.69dB at a noise figure of 10.29dB. Finally the mixer layout is designed using Microwind designing software within area 0.6mm2



Keywords: Gilbert mixer cell, LNA, LO, 0.18μm, VLSI technology, low power.


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