Comparative Study and Analysis of Universal Gates for Minimizing Power and Delay using Lector Technique. International Journal of Advanced Research in Computer Science, [S. l.], v. 5, n. 5, p. 29–33, 2017. DOI: 10.26483/ijarcs.v5i5.2148. Disponível em: https://www.ijarcs.info/index.php/Ijarcs/article/view/2148. Acesso em: 22 feb. 2026.