A SURVEY OF HARDWARE TROJAN DETECTION APPROACHES IN FPGA AND ASIC SYSTEMS

Abstract

Hardware security has become highly threatened by the high rate of semiconductor design and production globalization. The hardware Trojans have become a major danger that can negatively affect confidentiality, integrity, and availability of electronic systems due to the large number of ICs that are currently being produced in insecure facilities. These destructive changes can be introduced in any of the design stages or manufacturing processes and usually they spend many years being in dormancy before activation. This paper provides a wide overview of hardware Trojan detection methods in FPGA and ASIC systems. The paper discusses different detection methods, such as side-channel testing, optimization-based testing, machine learning-assisted testing and electromagnetic (EM)-based testing. It also addresses the weaknesses specific to FPGA and ASIC design and architecture, recent research trends and challenges, including the process variation, scalability and the complexity of the design of modern SoCs. The survey gives a complete account of the methodologies of detection, and the need to have secure design flows, trusted manufacture, and superior AI-based solutions defines the future hardware security solutions