POWER-AWARE DESIGN-FOR-TESTABILITY IN SEMICONDUCTOR DEVICES: A REVIEW OF ENERGY-EFFICIENT TESTING STRATEGIES

Abstract

The development of new testing techniques to prolong the life of semiconductors is seen as an important issue in integrated circuit (IC) design as new fabricated devices in the manufacture of semiconductors keep increasing in complexity and performance. Any excessive power use demonstrated in the testing may lead to yield loss, failure due to IR drop, thermal reliability issues, and overdesign. This review gives an outset exploration of the field of power-aware Design-for-Testability (DfT) methods and practices that are used to reduce the power consumption of designs under test (both dynamic as well as static power) as the test coverage of the design remains high. Important areas are low-power scan architectures, power savings via shift, scan chain reordering, compressed test patterns and power-limited automatic test pattern generation (ATPG). Emerging developments that are also discussed by the paper include 3D IC-aware DfT, AI-based test generation, and security-integrated low-power testing. The discussed strategies are assessed by their contribution to green chip production, thermal control and cost-effectiveness in modern System-on-Chip (SoC) designs. Additionally, another challenging issue under critical review is the power-thermal correlation, the increasing volume of test data, and test access overheads. The research opportunities ahead incorporate the concept of machine learning, real-time monitoring of power, context-sensitive test scheduling so that scalable, secure, and energy-aware semiconductor testing systems can be supported.