FAST: A Fast ASIP Synthesis Technique

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Manoj Kumar Jain


Interest in Application Specific Instruction Set Processors (ASIPs) has increased considerably in recent years. However, one of the
design metrics of embedded systems is the time to market of a product, which includes the design time of an embedded processor, is an
important consideration in the deployment of ASIPs. While the design time of an ASIP is very short compared to an ASIC it is longer than when
using a general purpose processor. There exist a number of tools which expedite this design process, and they could be divided into two: first,
tools that automatically generate HDL descriptions of the processor for both simulation and synthesis; and second, tools that generate instruction
set simulators for the simulation of the hardware models. While the first one is useful to measure the critical path of the design, die area, etc. they
are extremely slow for simulating real world software applications. At the same time, the instruction set simulators are fast for simulating real
world software applications, but they fail to provide information so readily available from the HDL models. The framework presented in this
paper, FAST, addresses this issue by integrating an automatic HDL generator with a well-known instruction set simulator. Therefore, embedded
systems designers who use our FAST framework will have the benefits of both a fast instruction set simulation and fast hardware synthesis at the
same time.



Keywords: Application Specific Instruction Set Processor (ASIP), simulation, synthesis, time to market, instruction set simulator


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