An Implementation of AES-128 Bit Encryption and Decryption Algorithm using Field Programmable Gate Array

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S.G. Sindhuja
Mrs.M.P.Flower Queen


:In today’s world most of the communication is done by using electronic media. Data security plays a vital role in such communication.
Hence, there is a need to protect data from many attacks. In this paper, to investigate hardware implementation of AES-128 cipher standard on
FPGA technology. In many network applications software implementations of cryptographic algorithms are slow and inefficient. To solve that
problems custom architecture in reconfigurable hardware was proposed to speed up the performance and flexibility of AES algorithm
implementation. The investigations involved simulations and synthesis of VHDL code utilizing Xilinx’s ISE 6 with the target device Spartan-II
.The main aim is to simulate the AES using Field Programmable Gate Array (FPGA) to achieve low cost, ease of implementation, high
flexibility including capability of frequent modifications of hardware, and low cost of the final product. The proposed design consumes less
power and area which is suitable battery driven mobile phones. NIST has selected Rijndael as the new Advanced Encryption Standard
(AES).The proposed architecture gives an reduction in area and increase in speed (throughput), reduces power consumption.



Keywords: Advanced Encryption Algorithm, FPGA, VHDL, encryption, decryption.


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