VLSI Implementation of Neural Network for Signal Compression & Decompression

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S.R. Kshirsagar
Prof. A.O.Vyas, Prof. A.D.Raut


Artificial intelligence is realized based on mathematical equations and artificial neurons. In the proposed design, our main focus is on the implementation of chip layout design for Feed Forward Neural Network Architecture (NNA) in VLSI for generic analog signal processing applications. The analog components like Gilbert Cell Multiplier (GCM), Adders, Neuron activation Function (NAF) are used in the implementation. This neural architecture is trained using Back propagation (BP) algorithm in analog domain with new techniques of weight storage. We are using 45nm CMOS technology for layout designing and verification of proposed neural network. The functionality of proposed design of neural network will be verified for analog operations like signal amplification and frequency multiplication.

Keywords: Gilbert cell, neuron activation function, neural network, VLSI, signal compression, signal decompression.


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