Design of Fault Tolearnt Reversible Full Adder/Subtarctor
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Abstract
Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design. The paper proposes the design of full Adder/Subtractor circuit using fault tolerant reversible logic gates. The design can work singly as a reversible Full Adder/Subtractor unit. It is a parity preserving reversible adder cell, that is, the parity of the inputs matches the parity of the outputs. The proposed parity preserving reversible adder can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit’s primary outputs. The proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.
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Keywords: Reversible gate, Feyman double gate, Fredkin gate, full adder, delay
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