A Multi Layer Technique for Performance Estimation for Asip Design Space Exploration

Abstract

Application Specific Instruction Set Processor or ASIPs are designed for a given application or for a set of applications. Since application set is limited, a better analysis of applications is possible which helps in identifying their special characteristics. These characteristics are used in ASIP design space exploration. This exploration suggests the optimum design which meets the stringent design constraints. The exploration is supported by estimation tools. Performance estimation is one such tool. Various researchers had suggested two types of techniques for performance estimation, namely, simulator based, and scheduler based approaches. They seem to be contrary to each other. This paper proposes that they are not contrary; in fact they are complimentary to each other. Since the scheduler based approaches use a very coarse model of architecture so they might not be as accurate as simulator based approaches. But the scheduler based approaches are very fast in nature and can handle a larger design space as they are not dependent on retargetable compilers and retargetable simulators. So we propose a new technique for performance estimation. A scheduler based approach should be used for an early design space exploration as the other approach is not suitable at this stage. This layer will suggest a few possible architectures suitable for input application. These architectures can be further analysed by a simulator based technique.

 

 

Keywords: Application Specific Instruction Set Processor (ASIP), simulation, synthesis, time to market, instruction set simulator, scheduler based, and performance estimation.