Piyush Kumar, Prof. Rahul Moud


Asynchronous FIFOs are often used to safely pass data from one clock domain to another asynchronous clock domain. Using a AFIFO to pass data from one clock domain to another clock domain requires multi -asynchronous clock design techniques. There are many ways to design a FIFO but still make it difficult to properly simulate and analyse the design.

FIFO can be either synchronous or asynchronous. The basic difference between them is that the entire operation of synchronous FIFO is dependent on the single clock whereas asynchronous FIFO have separate clock for the write operation and read operation.

This paper discusses about Asynchronous FIFO design and verification using Verilog and analyse the outputs using simulation performed in Questasim


Asynchronous FIFO

Full Text:



P Rajshekhar Rao, Manju Nanda., “Implementation and Verification of Asynchronous FIFO Under Boundary Condition”, International Journal of Engineering Research & Technology (IJERT) 2278-0181.

Mohini Akhare, Nitin Narkhede., “Design and Verification of Generic FIFO using Layered Test bench and Assertion Technique”, International Journal of Engineering and Advanced Technology (IJEAT). Issue-6, August 2019.

Lincy DF, S.Thenappan., “ASYNCHRONOUS FIFO DESIGN USING VERILOG”, International Research Journal of Engineering and Technology (IRJET), Volume: 07 Issue: 09, Sep 2020.

Dadhania Prashant C., “Designing Asynchronous FIFO”, International journal of information, knowledge and research in electronics and communication engineering, Volume 02, issue 02, pp-561-563



  • There are currently no refbacks.

Copyright (c) 2022 International Journal of Advanced Research in Computer Science