IMPLEMENTATION OF AES ALGORITHM ON FPGA FOR LOW AREA CONSUMPTION

Abstract

With the increasing number of internet and wireless communication users the demand for security measures to protect user data transmitted over open channels increases. So cryptography becomes important for such sensitive data which needs to be kept secured. AES can be considered as the most widely used modern symmetric key encryption standard. This paper propounds hardware implementation of AES to achieve less area and high speed. The proposed AES design supports 128 bit key length and 128 bit data blocks. Single register is used to store the round keys in each round of key expansion to reduce area consumption. The AES-128 is implemented on FPGA using Verilog language with the help of Xilinx ISE tool.