Neha Jain, Mayank Patel


The progresses and developments in the domain of semiconductor technology is about to take us into the era where there will be thousands of cores available on a System on Chip. The onset of 3D integration technologies has unlocked the doors of novel prospects for design of on-chip networks in SoCs attaining the higher efficiency in contrast to 2D integration by aptly adjusting the increased path lengths of 2D on chip archetypes. The intelligent mapping of the applications to core on a given NoC architecture can result into the improved system’s dynamic latency. The paper presents a heuristic based on branch and bound methodology for intelligent mapping of applications to cores in 3D Mesh NoC architecture. The experimental outcomes illustrate that average latency has been immensely decreased in the optimized 3D-Mesh on chip networks when compared against optimized 2D-Mesh network of the same size.


NOC, 3D IC, Mesh topology, Latency

Full Text:



Bernstein, K., Andry, P., Cann, J., Emma, P., Greenberg, D., Haensch, W., & Young, A. (2007, June). Interconnects in the third dimension: Design challenges for 3D ICs.In Proceedings of the 44th annual Design Automation Conference (pp. 562567).ACM.Choudhary, N., Gaur, M. S., &Laxmi, V. (2011).Energy Efficient Network Generation for Application Specific NoC. Global Journal of Computer Science and Technology, 11 (16).

Dick, R. P., Rhodes, D. L., & Wolf, W. (1998, March). TGFF: task graphs for free. In Proceedings of the 6th international workshop on Hardware/software codesign (pp. 97-101). IEEE Computer Society.

Ebrahimi, M., Daneshtalab, M., Liljeberg, P., Plosila, J.,

&Tenhunen, H. (2011, May). Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model.In Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on (pp. 7380).IEEE.

Feero, B. S., &Pande, P. P. (2009). Networks-onchip in a three-dimensional environment: A performance evaluation. Computers, IEEE Transactions on, 58 (1), 32-45.

Hassanpour, N., Khadem, P., Hessabi,S. (2013). A Task Migration Technique for Temperature Control in 3D NoCs. In 27th IEEE International Conference on Advanced Information Networking and Applications (AINA). Manuscript submitted for publication.

Hu, J., Marculescu, R. (2005). Design methodologies for application specific networks-on-chip. Ph.D. dissertation.Carnegie Mellon University.

Kahng, A. B., Li, B., Peh, L. S., &Samadi, K. (2009, April). Orion 2.0: A fast and accurate noc power andarea model for early-stage design space exploration. In Proceedings of the conference on Design, Automation and Test in Europe (pp. 423-428). European Design and Automation Association.

Rahmani, A. M., Latif, K., Liljeberg, P., Plosila, J., &Tenhunen, H. (2010, November). Research and practices on 3D networks-on-chip architectures. In NORCHIP, 2010 (pp. 1-6). IEEE.

Wadhwani, P., Choudhary, N. and Singh D. (2013). Energy Efficient Mapping in 3D Mesh Communication Architecture for NoC.International journal of Global Journal of Computer Science and Technology on Network, Web & Security (pp. 1-6).

Xu, Y., Du, Y., Zhao, B., Zhou, X., Zhang, Y., & Yang, J. (2009, February). A low-radix and low-diameter 3D interconnection network design.In High Performance Computer Architecture, 2009.HPCA 2009. IEEE 15th International Symposium on (pp. 30-42). IEEE.



  • There are currently no refbacks.

Copyright (c) 2017 International Journal of Advanced Research in Computer Science