Expanding the UVM Register Model towards Automation and Simplicity of Use

Abhishek Jain, Richa Gupta


The standard UVM register package contains built-in test sequences library which is used to perform most of the basic register and memory tests. These sequences are very useful at IP level verification but at SoC level verification, these sequences take very long time to run. Similarly, currently users require strong knowledge of SystemVerilog UVM language to use UVM_REG model. Some limitations in current UVM_REG package like no automatic data checking for memory accesses and limited support for memory burst operation were also seen. In this paper, we are describing how we addressed the above mentioned issues. We are accessing processor programmable registers and memories through a standard UVM_REG API. This API is aimed at writing simpler directed tests which require less or no SystemVerilog/UVM understanding. This API can be used to facilitate dumping register access for reuse from IP to SoC, or format outputs for use in ATE test vectors development etc. We also developed our own register/memory sequences to address the SoC level register and memory testing. Customized code is written to enhance the features of standard UVM_REG model. IP-XACT based tools are also developed to automatically generate all required verification environment files for using standard register model. Keywords: IP-XACT; Register Model; Register Sequences; SystemVerilog; Universal Verification Methodology (UVM); UVM_REG

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DOI: https://doi.org/10.26483/ijarcs.v8i3.3037


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