Power Harvesting and Area Efficient Clock Gating Method for a De-Composed MUX Controller
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Abstract
Multiplexer (MUX) is the key switching element to process and feed the data to various blocks of a computing core. Nowadays the data
size is of 64 bit or beyond. The use of MUX in ALU’s plays a prominent role to switch the correct logic path to further stage. Overall MUX
architecture for a larger data width uses more number of transistors and consumes unnecessary stand by or static power. To reduce the static power
consumption, the de-composed MUX with 2-1 MUX as a leaf cell is used as a tree like structure to build the top module. The Controller which
utilizes the PTL clock gating concept consumes nearly 20 μW low power than the AND gate as clocking gate. However the simulation results show
that the former one is nearly 100ns slower than the basic AND as clocking gate due to the so called trade off.
Keywords: Clock gating; low power; de-composed MUX; area optimization; dynamic; switching activity;
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