Optimal Value of Superscalar Factor in Superscalar Pipelined Processor Architecture

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Suresh Kumar Jha
Deepak Jangid, Rajesh Purohit


The performance of superscalar processor is affected by various parameters like superscalar factor, reservation station
architecture, size of reservation station, number of different functional units etc. The superscalar factor is the primary factor which
increases the IPS (instructions per cycle). Superscalar architecture supports the instruction level parallelism by issuing more than one
instruction per clock cycle i.e. increases the IPC. Increasing superscalar factor results in higher IPC. This paper intent to find the optimal
value of superscalar factor to which significant improvement in IPC can be achieved. The simulation performed using PSATSim v2.1
simulator with five different SPEC benchmark programs, considering both distributed and centralized reservation station architectures

Keywords: Superscalar, Distributed Reservation Station, Centralized Reservation Station, IPC, Execution Time, PSATSim/EdSATSim v2.1


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