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we propose a low power and area efficient two-cycle multiply-accumulate (2C-MAC) architecture which supports 2â€™s complement numbers, and includes accumulation guard bits and saturation circuitry. The first MAC pipeline stage contains only partial-product circuitry which is for generating partial product. And the second stage consists of sign-extension block, saturation unit and all other functionality. Proposed architecture does not need any additional cycles to generate the final result. It efficiently produces the addition of the accumulated value and the product in each cycle. And extend the new architecture to create a double throughput MAC, which can perform either multiply or multiply-accumulate operations.
Keywordsâ€”Arithmetic circuits, area efficient, low power, high speed adders, multiply-accumulate unit.
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