Performance Evaluation of Network on Chip Architecture using NS-2

Nayana Chandrakant Borase, Prof. Dr.G.R.Bamnote, Prof.M.A.Pund


A new chip design paradigm Network on Chip (NoC), proposed by many research groups is an important architectural choice for future System-on-Chip (SoCs). Various proposed Network on Chip (NoC) architecture attempts to address different component level architectures with specific interconnection network topologies and routing techniques, some of the topologies are CLICHE, Folded Torus, BFT, SPIN and Octagon.

Keywords: NoC, SoC, Network simulator, NoC architecture, soft error rates (SER), fault-tolerant designs, Network AniMator.

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